MDTLC Application Examples
Wire Over Plane
After a printed circuit board has been fabricated and assembled and is being tested, or sometimes even just after the design files have been irrevocably released for fabrication, a requirement to change one of the connections between components appears. This is done using a wire resembling wire-wrap wire. There are many names for this undesirable modification such as a strap, a blue wire, or a barnacle.
Just what is the transmission line impedance of this wire? Of course that depends on the wire and the surface over which it is run. Generally, it can be difficult to run a wire over a continuous copper plane, and some boards do not copper fill the outside layers. But for the purposes of this example, a ground fill plane is available on the top or bottom layer.
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2D Impedance
Calculator Program
Version 0.2.1.88
Time: Fri Feb 22
07:04:17 2008
GPL Version 2.0
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Simulation pix map
150 pixels high by 700 pixels wide.
316024 bytes
allocated for bmp.
Reading file
C:/Dev-Cpp/development/trimp/wire-flat-bigger.bmp ...
Image pixel dimensions:
500 high x 900 wide
INPUT PARAMETERS:
Layer Thick Specifications
Solder Mask Top 1.00
Opening w=0.0 offset=0.0
Copper Plane Top 1.30
Opening w=0.0 offset=0.0
Laminate Layer 1 5.00
Resin Content 64.3% 3.2-6.0
Signal Layer 1 1.35
4.0-6.0-4.0 Etchback=0.00
Laminate Layer 2 5.00
Resin Content 64.3% 3.2-6.0
Copper Plane Bottom 1.30
Opening w=0.0 offset=0.0
Layer Thick Er
Loss Tangent
Solder Mask Top 1.00
3.50 0.00200
Copper Plane Top 1.30
3.20
Laminate Layer 1 5.00
4.20 0.00120
Signal Layer 1 1.35
6.60 0.00120
Laminate Layer 2 5.00
4.20 0.00120
Copper Plane Bottom 1.30
3.20
DC
resistance by dimensions:
Rdc_trace_1= 125.69 Rdc_trace_2 = 125.69 milliohms/in 20C
DC resistance by pixel count:
Rdc_trace_1=
8.498 milliohm/in.
C
= 3.363 pF/in L =
7.315 nH/in.
Er
= 3.426 Loss_tan = 0.00073
Zo
= 46.640 Ohms Delay = 156.833 ps/in.
Log file save name:
mdtlc_08012225730.txt
Reading file
C:/Dev-Cpp/development/trimp/wire-flat-bigger-up2mil.bmp ...
Image pixel
dimensions: 500 high x 900 wide
INPUT PARAMETERS:
Layer Thick Specifications
Solder Mask Top 1.00
Opening w=0.0 offset=0.0
Copper Plane Top 1.30
Opening w=0.0 offset=0.0
Laminate Layer 1 5.00
Resin Content 64.3% 3.2-6.0
Signal Layer 1 1.35
4.0-6.0-4.0 Etchback=0.00
Laminate Layer 2 5.00
Resin Content 64.3% 3.2-6.0
Copper Plane Bottom 1.30
Opening w=0.0 offset=0.0
Layer Thick Er
Loss Tangent
Solder Mask Top 1.00
3.50 0.00200
Copper Plane Top 1.30
3.20
Laminate Layer 1 5.00
4.20 0.00120
Signal Layer 1 1.35
6.60 0.00120
Laminate Layer 2 5.00
4.20 0.00120
Copper Plane Bottom 1.30
3.20
DC resistance by dimensions:
Rdc_trace_1= 125.69 Rdc_trace_2 = 125.69 milliohms/in 20C
DC resistance by pixel count:
Rdc_trace_1=
8.498 milliohm/in.
C
= 2.110 pF/in L =
7.938 nH/in.
Er
= 2.333 Loss_tan = 0.00022
Zo
= 61.344 Ohms Delay = 129.408 ps/in.